In semiconductor integrated circuit fabrication, efforts for decreasing the size of an MOSFET.sub.-- (Metal-Oxide-Semiconductor Field Effect Transistor) consisting a semiconductor integrated circuit has been continued to obtain a highly integrated semiconductor circuit having excellent function.
As the result of such efforts, the technique for fabricating a semiconductor integrated circuit has been scaled down to a level of sub-micron level.
Only with the scaling down of semiconductor elements in horizontal direction as well as in vertical direction (proportional to the scaling down in horizontal direction), various characteristics of the elements can be balance. That is, for example in transistors, when the size of an element is to be decreased, making the distance between a source and a drain closer, un-desirable characteristic deterioration of the element can develop, typically creating the short channel effect.
To solve the short channel effect, horizontal dimensions (length of a gate) as well as vertical dimensions (thickness of a gate insulation film, junction depth etc.,) should be decreased, and according to which, the applied voltage should be lowered, the doping concentration of the substrate should be made denser, and particularly the doping profile of the channel region should be adjusted.
However, because the applied voltage of an element should match the required voltage of an appliance, and because the required voltage applied on electronic appliances using semiconductor elements has not been decreased yet, though the size of semiconductor elements keep decreasing, a problem arises. In the case of semiconductor elements, particularly NMOS transistors have a structure susceptible to hot carrier problems developed by electrons applied from source and accelerated by a sudden high electric field near a drain due to the short channel effect generated because the distance between a source and a drain is closer.
According to Chenming Hu et al., "Hot Electron-Induced MOSFET Degradation Model, Monitor and Improvement," IEEE Transactions on Electron Devices, Vol. ED-32, No, 2, 1985 pp. 375 to 385, the cause of instability due to hot carrier problem is a very high electric field near a drain junction caused by the short channel length and the high applied voltage. Accordingly, an LDD structure, an improvement of an existing NMOS element structure having a short channel length and susceptible to hot carrier problems, was suggested.
The features of an LDD structure disclosed by a reference paper [K. Saito et al., "A New Short Channel MOSFET with lightly doped Drain" Denshi Tsushin Rengo Taikai, 1978, pp. 220] is that an N.sub.-- region (low density impurity region) having a narrow width and self-aligned makes the high electric field near the drain junction spread out, preventing carriers (electrons) applied from a source from being accelerated even when high voltages are applied, thereby solving the instability of elements caused by hot carrier problem.
As research continues on the fabrication of elements having more than 1M DRAM class integration, many technologies for fabrication of MOSFETs having LDD structures have been suggested, of which an LDD forming method utilizing gate side wall spacers is the most typical. That which technology is used as a mass-production technology in most cases, until now.
Referring to FIG. 1, a method for fabrication of MOSFETs having conventional LDD structures is to be explained hereinafter.
First, when an NMOS is to be formed, as shown in FIG. 1(a), a gate oxidation film 3 is formed by an oxidation process on a p-type semiconductor substrate 1 divided into an active region and an element separation region by a field oxidation film 2.
Then, as shown in FIG. 1(b), a polysilicon layer 4 is formed on the gate oxidation film 3 as a conduction layer for forming a gate pole. A gate cap oxidation film 5 is formed on polysilicon layer 4.
Next, as shown in FIG. 1(c), photo resist 6 is deposited on the gate cap oxidation film 5, which photo resist 6 is exposed and developed by a photo etching process to form a desired gate pole pattern 6. Using the photo resist pattern as a mask, the gate cap oxidation film 5 and the polysilicon layer 4 are etched. Then, as shown in FIG. 1(d), a low density impurity region (n-region) 8 is formed by ion injecting 7 n-type impurities in low density ( to E13/cm2). Then, after the photo resist pattern 6 is removed, an oxidation film is formed on all over the surface of the substrate by a chemical vapor deposition method, and etched back to form side wall oxidation film 9 on the sides of the gate pole. Thereafter, to form high density source and drain regions, n-type impurities are ion injected 10 in high density (to E15/cm2) forming n+ source and drain regions 11 as shown in FIG. 1(e).
With the foregoing MOSFETs having LDD structures, when the integration of elements is advanced further making the channel length very short, it is hard to improve the short channel effect in which the threshold voltage of transistors is dropped due to the side effect from the low density impurity region and the punch through between the source and drain.
To overcome this problem, a MOSFET structure for preventing punch through between a source and a drain, includes a punch through prevention layer formed under the source and the drain as shown in FIG. 2.
The MOSFET having such a punch through prevention layer is formed by, in the foregoing MOSFET fabrication process of FIG. 1, after carrying out the process of FIG. 1(a), forming a punch through prevention layer A by ion injection into the substrate followed by the same processes shown in of FIG. 1(b) to FIG. 1(e).
However, the foregoing MOSFET structure has problems of increased parasitic capacitance and development of current leakage due to the direct contact of the punch through prevention layer formed for prevention of punch through between the source and the drain regions, with the high density source and drain regions.